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1/11 april 2003 n 24ma cmos output drive current n lvttl input thresholds n controlled skew between data and clock signals n lvds input-output up to 155 mhz n improved latch-up immunity up to 300ma description the STLVD112 is a low voltage differential to lvttl signal converter with enhanced loop-back and crosspoint features. the synchronous design allows a phase alignment between a clock and its data; this means a better ber (bit error rate) performance. the advanced 0.35m technology makes the STLVD112 suitable for data rates up to 200mbit. the main application field is sdh/sonet telecom infrastructure. the STLVD112 flexible switch architecture makes it easy to implement multiple protection schemes in stm1 access systems. thanks to the flexible multiplexing allowed, it becomes simple to redirect the data/clock signal coming from the faulty access card to the spare card. in normal mode the STLVD112 converts the differential data levels of the lvds and related clock signal from (to) the line interface in lvttl level signals to (from) the backpanel. in addition the switch functions prevent the equipment from line interface faults. in fact, it is possible to switch the signals coming from a different line interface to the local line interface or the signals from the local line interface to a different line interface. ordering codes ty pe temperature range package comments STLVD112btr -40 to 85 c tssop48 (tape & reel) 1000 parts per reel STLVD112ctr 0 to 70 c tssop48 (tape & reel) 1000 parts per reel STLVD112 high speed protection switch tssop
STLVD112 2/11 pin configuration
STLVD112 3/11 pin description truth tables for the five mux pln n symbol name and function 1, 6, 14, 22 vs1 main power supply 2 cksp_in lvttl clock input 3 datasp_in lvttl data input 4, 9, 13, 17, 21, 25, 36, 44, 48 gnd ground 5 losch control output 7 cksp_out lvttl clock output 8 datasp_out lvttl data output 10, 18, 31, 38 vs2 second power supply 11 ckch_in lvttl clock input 12 datach_in lvttl data input 15 ckprev_in lvttl clock input 16 dataprev_in lvttl data input 19 ckch_out lvttl clock output 20 datach_out lvttl data output 23 ckprev_out lvttl clock output 24 dataprev_out lvttl data output 26, 30, 37, 43 n.c. not connected 27 kloop_sp control input 28 kloop_i control input 29 ki control input 32 datainb lvds data input - 33 dataina lvds data input + 34 ckinb lvds clock input - 35 ckina lvds clock input + 39 ckoutb lvds clock output - 40 ckouta lvds clock output + 41 dataoutb lvds data output - 42 dataouta lvds data output + 45 lossp control output 46 losi control input 47 losprev control input inputs output ki kloop_sp kloop_i data_out low x x datach_in high x x datasp_in inputs output ki kloop_sp kloop_i datach_out x x low datain x x high datach-in
STLVD112 4/11 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. recommended operating conditions inputs output ki kloop_sp kloop_i datasp_out low low x dataprev_in high low x data_in x high x datasp_in inputs output ki kloop_sp kloop_i losch x x low losi x x high low inputs output ki kloop_sp kloop_i lossp low low x losprev high low x losi x high x low symbol parameter value unit vs1, vs2 supply voltage -0.3 to 4.6 v vs2 supply voltage -0.3 to (vs1 + 0.3) v v i dc input voltage -0.3 to (vs1 + 0.3) v v o dc output voltage -0.3 to (vs1 + 0.3) v iik dc input diode clamp current 20 ma iok dc output diode clamp current 20 ma i o dc output current 50 ma t l lead temperature (10sec) 300 c t stg storage temperature range -65 to 150 c symbol parameter value unit vs1, vs2 supply voltage 3 to 3.6 v vs2 supply voltage 3 to (vs1 + 0.3) v v i dc input voltage 0 to vs1 v v o dc output voltage 0 to vs1 v top operating temperature -45 to 85 c dt/dv maximum input rise and fall time 10 ns/v
STLVD112 5/11 electrical characteristics (over recommended operating conditions, unless otherwise noted. all typical values are at t a =25c and v s1 ,v s2 =3.3v) lvds driver electrical characteristics (over recommended operating conditions, unless otherwise noted. all typical values are at t a =25c and v s1 ,v s2 =3.3v) lvds receiver electrical characteristics (over recommended operating conditions, unless otherwise noted. all typical values are at t a =25c and v s1 ,v s2 =3.3v) symbol parameter test conditions value unit min. typ. max. v ol low level output voltage i out = 24 ma 0.2 0.4 v v oh high level output voltage i out =24ma v si -0.5 v si -0.3 v v il low level input thresholds v out = 0.1v or v s1 - 0.1 0 0.8 v v ih high level input thresholds v out = 0.1v or v s1 - 0.1 2 v si v i in input leakage current v in = gnd or v cc -1 1 a i cc quiescent supply current v in = gnd or v cc 15 ma f clock = 155mhz 110 symbol parameter test conditions value unit min. typ. max. v od differential output voltage r l = 100 w 247 364 454 mv d v od change in differential output voltage between logic states -50 50 mv v oc(ss) steady-state common-mode output voltage 1 1.15 1.30 v d v oc(ss) change in steady-state common- mode output voltage between logic state -50 50 mv d v oc(pp) peak-to-peack common-mode output voltage 100 150 mv i sc short circuit output current v o(y) or v o(z) = 0 -24 -4 ma v od =0 12 i off power off output current v cc =0,v o = 2.4v -1 1 a symbol parameter test conditions value unit min. typ. max. v ith+ positive-going differential input voltage threshold 100 mv v ith- negative-going differential input voltage threshold -100 mv |v id | magnitude of differential input voltage 0.1 0.6 v v ic common-mode input voltage 0.5 |v id | 2.4-0.5 |v id | v v cc -1
STLVD112 6/11 lvds switching timing characteristics (over recommended operating conditions, unless otherwise noted. all typical values are at t a =25c and v s1 ,v s2 =3.3v) ac lvttl in lvttl out (over recommended operating conditions, unless otherwise noted. all typical values are at t a =25c and v s1 ,v s2 =3.3v) ac control output (lossp, losch) (over recommended operating conditions, unless otherwise noted. all typical values are at t a =25c and v s1 ,v s2 =3.3v) ac lvttl in lvds out (over recommended operating conditions, unless otherwise noted. all typical values are at t a =25c and v s1 ,v s2 =3.3v) symbol parameter test conditions value unit min. typ. max. t w minimum pulse width <1 ns symbol parameter test conditions value unit min. typ. max. t plh propagation delay time, low-to-high- level output (50% to 50%) measured with v in =0 to 2.5v, f clock = 1mhz, f data = 0.5mhz t r =t f = 0.4ns, +duty cycle=50% t phl ,t plh are referred to output clock transitions. 2.4 3.9 5.6 ns t phl propagation delay time, high-to-low- level output (50% to 50%) 2.5 4.2 5.3 ns t tlh transition time, low-to-high-level output (10% to 90%) 0.7 1.3 1.6 ns t thl transition time, high-to-low-level output (90% to 10%) 0.7 1.1 1.3 ns f opr operative frequency 100 155 200 mhz symbol parameter test conditions value unit min. typ. max. t plh propagation delay time, low-to-high- level output (50% to 50%) measured with v in =0 to 2.5v, f clock = 1mhz, f data = 0.5mhz t r =t f = 0.4ns, +duty cycle=50% t phl ,t plh are referred to output clock transitions. 2.4 3.6 4.4 ns t phl propagation delay time, high-to-low- level output (50% to 50%) 2.4 3.4 4.2 ns t tlh transition time, low-to-high-level output (10% to 90%) 0.9 1.9 2.3 ns t thl transition time, high-to-low-level output (90% to 10%) 0.7 1.0 1.2 ns symbol parameter test conditions value unit min. typ. max. t plh propagation delay time, low-to-high- level output (50% to 50%) measured with v in =0 to 2.5v, f clock = 1mhz, f data = 0.5mhz t r =t f = 0.4ns, +duty cycle=50% t phl ,t plh are referred to output clock transitions. 2.8 3.8 4.7 ns t phl propagation delay time, high-to-low- level output (50% to 50%) 2.6 3.4 4.1 ns t tlh transition time, low-to-high-level output (20% to 80%) 0.4 0.5 0.6 ns t thl transition time, high-to-low-level output (80% to 20%) 0.4 0.6 0.7 ns f opr operative frequency 100 155 200 mhz
STLVD112 7/11 ac lvds in lvttl out (over recommended operating conditions, unless otherwise noted. all typical values are at t a =25c and v s1 ,v s2 =3.3v) lvttl in lvttl out (v cc =3to3.6vt a = -45 to 80c, unless otherwise noted. typical values are at t a =25c) lvttl in lvds out (over recommended operating conditions, unless otherwise noted. all typical values are at t a =25c and v s1 ,v s2 =3.3v) lvds in lvttl out (over recommended operating conditions, unless otherwise noted. all typical values are at t a =25c and v s1 ,v s2 =3.3v) symbol parameter test conditions value unit min. typ. max. t plh propagation delay time, low-to-high- level output (50% to 50%) v diff = 400mv measured with v icm =1.2v, f clock = 1mhz, f data = 0.5mhz t r =t f = 0.4ns, +duty cycle=50% t phl ,t plh are referred to output clock transitions 4.3 5.6 6.9 ns t phl propagation delay time, high-to-low- level output (50% to 50%) 4.1 5.4 6.7 ns t tlh transition time, low-to-high-level output (10% to 90%) 0.7 0.9 1.1 ns t thl transition time, high-to-low-level output (90% to 10%) 0.8 1.0 1.3 ns f opr operative frequency 100 155 200 mhz symbol parameter test conditions value unit min. typ. max. t s setup time f = 10mhz, v icm = 1.2 v v diff = 400mv, v inttl = 0 to 2.5v 1ns t h- hold time 1 ns symbol parameter test conditions value unit min. typ. max. t s setup time f = 10mhz, v icm = 1.2 v v diff = 400mv, v inttl = 0 to 2.5v 1ns t h- hold time 1 ns symbol parameter test conditions value unit min. typ. max. t s setup time f = 10mhz, v icm = 1.2 v v diff = 400mv, v inttl = 0 to 2.5v 1.5 ns t h- hold time 1 ns
STLVD112 8/11 logic diagram
STLVD112 9/11 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.006 a2 0.9 0.035 b 0.17 0.27 0.0067 0.011 c 0.09 0.20 0.0035 0.0079 d 12.4 12.6 0.488 0.496 e 8.1 bsc 0.318 bsc e1 6.0 6.2 0.236 0.244 e 0.5 bsc 0.0197 bsc k0? 8?0? 8? l 0.50 0.75 0.020 0.030 tssop48 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 7065588c
STLVD112 10/11 dim. mm. inch min. typ max. min. typ. max. a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n 60 2.362 t 30.4 1.197 ao 8.7 8.9 0.343 0.350 bo 13.1 13.3 0.516 0.524 ko 1.5 1.7 0.059 0.067 po 3.9 4.1 0.153 0.161 p 11.9 12.1 0.468 0.476 tape & reel tssop48 mechanical data
STLVD112 11/11 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com

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